78 lines
2.0 KiB
NASM
78 lines
2.0 KiB
NASM
; SST_CPUCache_x86-64.asm
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; Author: Patrick Baggett <ptbaggett@762studios.com>
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; Created: 12/23/2011
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;
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; Purpose:
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;
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; 64-bit assembly for x86 CPU cache functions for the SysV ABI. Assembles with YASM 1.1/NASM 2.0+
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;
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; License:
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;
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; This program is free software. It comes without any warranty, to
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; the extent permitted by applicable law. You can redistribute it
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; and/or modify it under the terms of the Do What The Fuck You Want
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; To Public License, Version 2, as published by Sam Hocevar. See
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; http://sam.zoy.org/wtfpl/COPYING for more details.
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; Win64 and UNIX calling conventions differ for x64-64. I know, it's absurd.
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; Because of this, there are separate implementation for Win64 and x64-64 UNIX (Linux, *BSD, Solaris, MacOS X, etc.)
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; Here is the break down:
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;
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; REGISTER | Win64 | UNIX
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;-----------+-----------+----------
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;rax | Retval | Retval
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;rsi | Not used | 1st arg
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;rdi | Not used | 2nd arg
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;rcx | 1st arg | 3rd arg
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;rdx | 2nd arg | 4th arg
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;r8 | 3rd arg | 5th arg
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;r9 | 4th arg | 6th arg
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[bits 64]
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[segment .text]
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; ELF symbol names
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[global SST_OS_GetCacheLineSize]
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[global SST_OS_FlushDCRange]
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[global SST_OS_InvalidateICRange]
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[global SST_OS_SyncCache]
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;uint32_t SST_OS_GetCacheLineSize()
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;no args, so win64 and unix abis are the same
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SST_OS_GetCacheLineSize:
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push rbx
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mov eax, 0x80000006 ;Cache info command
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cpuid
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movzx rax, cl ;ECX bits 0-7 = L2 cache line size (TODO: what about L1?)
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pop rbx
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ret
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;SST_OS_InvalidateICRange(void* base, size_t range)
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SST_OS_InvalidateICRange:
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;A jmp instruction is sufficient. x86 CPUs have self-snooping caches.
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jmp do_serialize
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do_serialize:
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ret
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; void SST_OS_SyncCache()
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SST_OS_SyncCache:
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mfence
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ret
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;void SST_OS_FlushDCRange(void* base, size_t range)
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SST_OS_FlushDCRange:
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call SST_OS_GetCacheLineSize ;Get the cache line size
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dc_flush_more1: ;do {
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clflush [rcx]
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add rcx, rax ;base += cache_line_size
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sub rdx, rax ;range -= cache_line_size
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cmp rcx, 0
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jg dc_flush_more1 ; } while(range > 0)
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ret |