77 lines
1.8 KiB
NASM
77 lines
1.8 KiB
NASM
; SST_CPUCache_x86.asm
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; Author: Patrick Baggett <ptbaggett@762studios.com>
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; Created: 12/23/2011
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;
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; Purpose:
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;
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; 32-bit assembly for x86 CPU cache functions. Assembles with YASM 1.1/NASM 2.0+
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;
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; License:
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;
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; This program is free software. It comes without any warranty, to
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; the extent permitted by applicable law. You can redistribute it
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; and/or modify it under the terms of the Do What The Fuck You Want
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; To Public License, Version 2, as published by Sam Hocevar. See
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; http://sam.zoy.org/wtfpl/COPYING for more details.
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[bits 32]
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[segment .text]
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; Win32 symbol names
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[global _SST_OS_GetCacheLineSize]
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[global _SST_OS_FlushDCRange]
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[global _SST_OS_InvalidateICRange]
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[global _SST_OS_SyncCache]
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; ELF symbol names
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[global SST_OS_GetCacheLineSize]
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[global SST_OS_FlushDCRange]
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[global SST_OS_InvalidateICRange]
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[global SST_OS_SyncCache]
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;uint32_t SST_OS_GetCacheLineSize()
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_SST_OS_GetCacheLineSize:
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SST_OS_GetCacheLineSize:
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push ebx
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mov eax, 0x80000006 ;Cache info command
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cpuid
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movzx eax, cl ;ECX bits 0-7 = L2 cache line size (TODO: what about L1?)
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pop ebx
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ret
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;void SST_OS_FlushDCRange(void* base, size_t range)
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_SST_OS_FlushDCRange:
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SST_OS_FlushDCRange:
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call SST_OS_GetCacheLineSize ;Get the cache line size
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mov edx, [esp+4] ;edx = base
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mov ecx, [esp+8] ;ecx = range (in bytes)
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dc_flush_more: ;do {
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clflush [edx]
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add edx, eax ;base += cache_line_size
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sub ecx, eax ;range -= cache_line_size
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cmp ecx, 0
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jg dc_flush_more ; } while(range > 0)
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ret
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;SST_OS_InvalidateICRange(void* base, size_t range)
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_SST_OS_InvalidateICRange:
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SST_OS_InvalidateICRange:
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;A jmp instruction is sufficient. x86 CPUs have self-snooping caches.
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jmp do_serialize
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do_serialize:
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ret
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; void SST_OS_SyncCache()
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_SST_OS_SyncCache:
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SST_OS_SyncCache:
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mfence
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ret |